1. Field of the Invention
The present invention generally relates to a feedback controlled transconductance switching power amplifier particularly adapted for driving inductive loads, and more particularly, to a switching power amplifier for generating control pulses having a guaranteed minimum switching interval.
2. Discussion of the Background
Switching power amplifiers are distinguished from more conventional linear power amplifiers in that the output voltage, rather than being continuously variable over some wide range, is restricted to essentially two fixed levels. The purpose of this restriction is to minimize power losses in the output devices which are generally some kind of transistor device.
Linear amplifiers achieve a variable output voltage by controlling the resistance of the output transistors which are in series with a load between a fixed power supply and ground. Thus, at any output voltage intermediate between the power supply voltage and the ground, the output transistors must dissipate power resistively.
Switching power amplifiers avoid power dissipation by only operating the output transistors in a saturated "on" state having low resistance or in a "off" state having a very high resistance. Power dissipation in these amplifiers occurs primarily while the transistors are switching from one state to another, with some power being dissipated in the "on" state due to the non-zero on-resistance of the transistors. Because some of the power dissipation in these amplifiers occurs during the state transitions, it is clear that the efficiency relies on keeping the switching rate below some threshold which depends upon the switching characteristics of the output transistors.
The most widely used switching power amplifier is the pulse width modulated or PWM amplifier. This amplifier is a voltage-to-voltage amplifier, generally employing no feedback. It can be used to produce a transconductance amplifier if it is designed with a high gain and placed in a current comparative feedback loop.
The linearization scheme employed in PWM amplifiers is to rapidly switch the voltage applied to the load between two fixed levels, V.sub.1 and V.sub.2, in such a manner that the average voltage across the load is equal to a desired voltage. This is accomplished by comparing the input voltage to a high frequency triangle wave of fixed amplitude and frequency. As long as the reference triangle wave is smaller than the input voltage, the output devices are switched to apply V.sub.1 to the load where V.sub.1 is greater than V.sub.2. When the reference triangle wave rises above the input voltage, the output devices are switched to apply voltage V.sub.2 to the load.
A principal drawback of PWM amplifiers is their high complexity. In addition, when used in a current comparative feedback loop, the resulting system must be carefully compensated to ensure stability when driving inductive loads. This compensation tends to restrict the useable bandwidth of the overall amplifier.
A similar approach to building a switching transconductance amplifier for driving inductive loads is a "bang-bang" controlled system with a fixed sampling rate. This scheme involves driving the output amplifiers directly with the current comparator signal such that when the output current is larger than the requested current, the output transistors switch the output voltage to a "low" value and when the output current is less than the requested current, the output transistors switch the output voltage to a "high" value. In order to restrict the switching to a rate which provides high efficiency, a sample-and-hold device is inserted between the comparator and the output. This device is driven by a periodic clock. At the beginning of each clock period, the sample-and-hold device transfers the state of the comparator to the output devices. This state is then retained for the remainder of the clock period, and in this manner, the minimum switching rate is fixed by the clock.
Fixed sampling rate control can be implemented with a fairly simple circuit giving it a substantial advantage over PWM control. Its primary drawback is that this control scheme produces aliasing of signals having frequencies in excess of half the sampling frequency because the sampling times are fixed. This produces significant harmonic and crossover distortion.
Another approach which is similar to fixed sampling rate control is hysteretic control. Here, a small amount of hysteresis is added to the comparator so that rather than switching to a positive state precisely when the error between requested and actual currents becomes positive and switching to a negative state precisely when the error becomes negative, the positive transition is delayed until the error reaches some threshold value. When the amplifier is driving an inductive load, these voltage values yield a time delay due to the integrating effect of the load. Thus, a fixed period sample-and-hold device is apparently not required to control the minimum switching rate: the output of the comparator can drive the output devices directly with no intervening logic
The circuit required to implement hysteretic control is even simpler than that required for fixed sampling rate control in that the arrangement dispenses with the clock and the sample-and-hold device at the expense of only a few resistors needed to produce the desired hysteresis. The absence of a fixed sampling rate results in an asynchronous configuration which greatly reduces harmonic and crossover distortion. The most apparent drawback to this design is that the switching rate will depend not only on the amount of hysteresis designed into the circuit, but also on the load impedance and the power supply voltages. Consequently, the amplifier must be tuned to the load in order to ensure that the switching rate does not exceed the maximum allowed for the output stage while remaining high enough to yield good bandwidth. A more insidious problem inherent in hysteretic control is that it can produce very short control pulses if the reference signal changes rapidly. This is a particular problem in the presence of noise in the reference signal. In the simple analysis, short control pulses will only seem to degrade the efficiency of the amplifier, but if the output is an H-bridge, short pulses may cause device failure.
Yet another approach is the pulse shaping configuration, wherein a pulse shaper is positioned between the comparator and output devices to guarantee a minimum switching interval, i.e., no short pulses. The disadvantages of this arrangement are that it exhibits moderately severe amplitude distortion and the output waveform always lags input reference in phase and magnitude. Further, stretching very short pulses to a given time interval causes deadband behavior in the output waveform.
Patents which disclose arrangements similar to those discussed above include U.S. Pat. Nos. 3,560,829, 4,779,183, 4,517,522, 4,288,738, 4,471,278, 3,745,477 and 4,636,711.